Modeling, synthesis, and rapid prototyping with the Verilog HDL
| Main Author: | Ciletti |
|---|---|
| Format: | Open Shelf |
| Published: |
Upper Saddle River, N.J:
Prentice Hall,
c1999.
|
| Subjects: |
| LEADER | 00584pamja2200181 4500 | ||
|---|---|---|---|
| 001 | 0000038300_0011 | ||
| 005 | 20150326090000.0 | ||
| 002 | 002229 | ||
| 020 | |a 0139773983 | ||
| 090 | 0 | 0 | |a TK7885.7 |b C554 1999 |
| 100 | 0 | |a Ciletti | |
| 245 | 0 | 0 | |a Modeling, synthesis, and rapid prototyping with the Verilog HDL |c Michael D. Ciletti |
| 260 | |a Upper Saddle River, N.J: |b Prentice Hall, |c c1999. | ||
| 300 | |a xxii,727p: |b ill; |c 25cm. | ||
| 504 | |a Includes bibliographical references and index | ||
| 650 | 0 | 0 | |a Verilog (Computer hardware description language) |
| 999 | 0 | 0 | |a 004190 |
| 999 | |a 0000046382 | ||